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Bharath Shashidhar

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5th June 201711th August 2020 bhs011

Installing OpenSource EDA tools on ubuntu

Linux, Technology

ASIC Design Flow requires many EDA tools and industry uses some of the advanced EDA tools. For expanding your knowledge on these tools and the

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5th June 201711th August 2020 bhs011

Setting up SSH Server on local machine – Ubuntu

Linux, Technology

There is way where a local machine can be accessed using ssh once you install OpenSSH.  Both the host (server) and Client must be in

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2nd May 20171st April 2020 bhs011

Verification Suite using SystemVerilog – Functional Coverage – v2.0

Technology, Verification

Systemverilog verification suite of synchronous RAM along with functional coverage, my v1.0 suite can be found here `timescale 1 ns/10 ps module memory(input logic clock ,

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9th March 201711th August 2020 bhs011

Parallel Programming – Part 1

Image Processing, Parallel Processing, Technology

I recently started Parallel programming course on Udacity and this blog is my journey through the course. My fascination with new and upcoming technologies goes

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24th January 201711th August 2020 bhs011

Cache Simulator v1.0

Algorithm, C, Simulator, Technology

Cache simulator is implemented in C. It takes several parameters describing the cache and a trace file describing the memory access for a specific program. The

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10th September 20161st April 2020 bhs011

SAP-1 (Simple As Possible 1) Microprocessor – Part 4

Design - Verilog, Technology

The Testbench and Results The test program was stored in RAM of SAP-1 microprocessor, Load contents of memory location 9H into accumulator 9H contains 01H.

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10th September 2016 bhs011

SAP-1 (Simple As Possible 1) Microprocessor – Part 3

Design - Verilog, Technology

Control unit is the heart of any microprocessor, the SAP-1 microprocessor is reset using the clr signal. The program counter is reset to 0000 and

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10th September 2016 bhs011

SAP-1 (Simple As Possible 1) Microprocessor – Part 2

Design - Verilog, Technology

This is continuation of my work in implementing the SAP1 processor. This part contains sap1 architecture. Accumulator It is the buffer register which stores intermediate

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8th September 20161st April 2020 bhs011

SAP-1 (Simple As Possible 1) Microprocessor – Part 1

Design - Verilog, Technology

Simple As Possible 1 Architecture Block Diagram SAP-1 is a primitive microprocessor architecture and is good step towards understanding microprocessor working, interaction with memory and

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30th August 2016 bhs011

Verification Suite using SystemVerilog

Technology, Verification

  The device under test is the synchronous RAM, `timescale 1 ns/10 ps module memory(input logic clock , // Clock input logic [7:0] address ,

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I'm a FPGA design engineer experienced in Very High speed interfaces, SDR, Signal Processing and embedded system design. This blog is dedicated to capture my trials and experiments.

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Recent Posts

  • Installing OpenSource EDA tools on ubuntu
  • Setting up SSH Server on local machine – Ubuntu
  • Verification Suite using SystemVerilog – Functional Coverage – v2.0
  • Parallel Programming – Part 1
  • Cache Simulator v1.0

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  • Parallel Processing
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  • Verification
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