SAP-1 (Simple As Possible 1) Microprocessor – Part 3

Control unit is the heart of any microprocessor, the SAP-1 microprocessor is reset using the clr signal. The program counter is reset to 0000 and last instruction in the instruction register is wiped off. Three states are common to all the signals, T1 states enables reading of the program counter, which acts as the address of the RAM for the execution of stored program. The first four bits are the instruction and the last four bits are the address, with the contents of RAM. The first four bits are processed to generate the control signal based on the instruction and the state. This computer has only 5 instructions. So this makes a good project for starters to program in verilog and understand the working of a microprocessor (SAP-1).

State Machine

module fsm(
input clk,
input clr,
output [6:1] state);

reg [6:1] state;


initial begin
    state = 6'b000000;
    end

always @(posedge clk)
    begin
        if(!clr)
        begin
            state <= 6'b000001;
        end

        else begin
            case(state)
                6'b000000: state = 6'b000001;
                6'b000001: state = 6'b000010;
                6'b000010: state = 6'b000100;
                6'b000100: state = 6'b001000;
                6'b001000: state = 6'b010000;
                6'b010000: state = 6'b100000;
                6'b100000: state = 6'b000001;
            endcase
        end
    end



endmodule

 

Control Unit

SAP1 has a hardwired control unit, which generates 12 control signals based on the state and the instruction. The control signals are CP, EP, LM, CE, LI, EI, LA, EA, SU, EU, LB and LO.

module cu(
input [3:0] irin,       //IR input
input clk,
input clr,
input [6:1] state,          //State from fsm

output EP,              //Enable PC                                     + Program counter       + active(high)
output EA,              //Enable Accumulator                            + Accumulator           + active(high)
output SU,              //Sum or Diff : ALU                             + ALU                   + active(high)
output EU,              //Enable ALU output                             + ALU                   + active(high)
output LA,              //Latch Accumulator output                      + Accumulator           + active(low)
output LO,              //Latch Output Register Output                  + Output Register       + active(low)
output LB,              //Latch B register Output                       + B register            + active(low)
output CP,              //Count                                         + Program counter       + active(high)
output EI,              //Enable Instruction Register                   + Instruction Register  + active(low)
output LI,              //Latch Instruction Register Output             + Instruction Register  + active(low)
output LM,              //Latch Memory Address Register Output          + Memory Address Reg    + active(low)
output CE);             // Chip enable                                  + RAM                   + active(low)



reg EP;
reg EA;
reg SU;
reg EU;
reg LA;
reg LO;
reg LB;
reg CP;
reg EI;
reg LI;
reg LM;
reg CE;

initial begin
    CP=0;
    EP=0;
    LM=1;
    CE=1;
    LI=1;
    EI=1;
    LA=1;
    EA=0;
    SU=0;
    EU=0;
    LB=1;
end


always @(negedge clk)
    begin
        if(state == 6'b000001)
        begin
            CP=0;
            EP=1;                                       //Enabling Program Counter and MAR  
            LM=0;                                       //This loads the address in the PC to MAR
            CE=1;
            LI=1;
            EI=1;
            LA=1;
            EA=0;
            SU=0;
            EU=0;
            LB=1;
            LO=1;
        end

        else if(state == 6'h02)
        begin
             CP=1;                                                  //Incrementing the PC by 1
             EP=0;
             LM=1;

        end

        else if(state == 6'b000100)
        begin
             CP=0;                                                  //Enabling RAM and Instruction Register
             EP=0;                                                  //Reads microinstruction into IR, WHich send only OPCODE(upper nibble) into Control unit
             LM=1;
             CE=0;
             LI=0;
        end

        else if(state == 6'b001000)                                 // State 4
        begin
               LI=1;
               CE=1;
            if(irin == 4'b0000)                                     // LOAD instruction
            begin
                EI=0;
                LM=0;
            end

            else if(irin == 4'b0001)                                // ADD instruction
            begin
                EI = 0;
                LM = 0;
            end

            else if(irin == 4'b0010)                                // SUBTRACT instruction
            begin
                EI = 0;
                LM = 0;
            end
 else if(irin == 4'b0010)                                // SUBTRACT instruction
            begin
                EI = 0;
                LM = 0;
            end

            else if(irin == 4'b1110)                                // OUT instruction
            begin
                EA = 1;
                LO = 0;
            end

            else if(irin == 4'b1111)                                // HALT instruction
            begin
                $stop;
            end

        end

     else if(state == 6'b010000)                                        // State 5
        begin

            if(irin == 4'b0000)                                     // LOAD instruction
            begin
                LA=0;
                CE=0;
                EI=1;
                LM=1;
            end

            else if(irin == 4'b0001)                                // ADD instruction
            begin
                EI = 1;
                LM = 1;
                CE = 0;
                LB = 0;
            end

            else if(irin == 4'b0010)                                // SUBTRACT instruction
            begin
                EI = 1;
                LM = 1;
                LB = 0;
                CE = 0;
            end

            else if(irin == 4'b1110)                                // OUT instruction
            begin

            end

            else if(irin == 4'b1111)                                // HALT instruction
            begin

            end
     end

     else if(state == 6'b100000)                                        // State 6
        begin

            if(irin == 4'b0000)                                     // LOAD instruction
            begin
                CP=0;
                EP=0;
                LM=1;
                CE=1;
                LI=1;
                EI=1;
                LA=1;
                EA=0;
                SU=0;
                EU=0;
                LB=1;
                LO=1;
            end

            else if(irin == 4'b0001)                                // ADD instruction
            begin
                CE = 1;
                LB = 1;
                LA = 0;
                EU = 1;
                SU = 0;
            end

            else if(irin == 4'b0010)                                // SUBTRACT instruction
            begin
                EU = 1;
                LA = 0;
                LB = 1;
                CE = 1;
                SU = 1;
            end

            else if(irin == 4'b1110)                                // OUT instruction
            begin

            end

            else if(irin == 4'b1111)                                // HALT instruction
            begin

            end

        end
    end
endmodule

 

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