SAP-1 (Simple As Possible 1) Microprocessor – Part 2

This is continuation of my work in implementing the SAP1 processor. This part contains sap1 architecture.

Accumulator

It is the buffer register which stores intermediate results of the alu.

module accumulator(
input LA,                       // Latch data into acc
input EA,                       // Enable output
input clk,
input [7:0] datain,
output [7:0] dataout, aluout);  //dataout -> Data out to WBUS
                                //aluout -> Alu out


reg [7:0] aluout;

initial begin
    aluout = 8'h00;
    end

assign dataout = (EA)? aluout : 8'hzz;

always @(posedge clk)
    begin
        if(!LA)
        begin
            aluout <= datain;
        end
    end

endmodule

 

B register

Buffer register to hold the second operand.

module breg(
input LB,
input clk,
input [7:0] datainb,
output [7:0] baluout);


reg [7:0] baluout;

initial begin
    baluout <= 8'hzz;
end

always @(posedge clk)
    begin
        if(!LB)
        begin
        baluout <= datainb;
        end
    end

endmodule

 

Adder or Subtractor unit

This is the  module which does addition or subtraction (as the same suggests)

module alu (
input SU,           //Sum active(low)    Diff active(high)
input EU,           //Output available on bus active(high)
input [7:0] A,      //Accumulator Input
input [7:0] B,      //B register input
output [7:0] S);    //Output



assign S = (EU)? ((SU)? (A-B):(A+B)): 8'hzz;


endmodule

 

Out Register

The register which stores the output.

module outreg(
input [7:0] outdatain,
input LO,
input clk,
output [7:0] result);

reg [7:0] result;

initial begin
    result = 8'hzz;
end

always @(posedge clk)
    begin
        if(!LO)
        begin
            result = outdatain;
        end
    end

endmodule

 

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