Simple As Possible 1 Architecture Block Diagram
SAP-1 is a primitive microprocessor architecture and is good step towards understanding microprocessor working, interaction with memory and IO. It has a very limited instruction set. The basic features are
- W bus : A single 8 bit bus for address and data transfer.
- 16 Bytes memory (RAM)
- Registers are accumulator and B-register each of 8 bits.
- Program counter initializes from 0000 to 1111 during program execution.
- Memory Address Register (MAR) to store memory addresses.
- Adder, Sub-tractor for addition and subtraction instructions.
- A hardwired control unit.
- 6 machine state reserved for each instruction.
- The instruction format of SAP-1 Computer is (XXXX) (XXXX). Upper nibble is the opcode and lower nibble is the address.
Instruction Set[table “1” not found /]
Counts from 0000 to 1111, this is used as address for next instruction.
module pc( input CP, //Count input clk, input clr, input EP, //Enable PC -> latch PC output to bus output [3:0] pcout); reg [3:0] nextPc; initial begin nextPc <= 4'b0000; end always @(posedge clk) begin if(CP) begin nextPc <= nextPc+1; end if(!clr) begin nextPc <= 4'b0000; end end assign pcout = (EP)? nextPc : 4'hz; endmodule
Memory Address Register
It stores the memory address from which the data will be fetched to the CPU.
module mar( input LM, //Latch mar active(low) input clk, input [3:0] wdatain, output [3:0] address, output OE); reg tempOE; reg [3:0] address; initial begin address <= 4'hz; tempOE <=1; end always @(posedge clk) begin if(!LM) begin address <= wdatain; tempOE <=0; end end assign OE = tempOE; endmodule
Asynchronous RAM of capacity 16 bytes, It stores the program to be executed and is written into from the CPU.
module mem( input WE, //write enable - active (low) + No write to RAM in SAP1, always 1 input RE, //Read enable - active (low) input CE, //Chip Enable inout [7:0] data, input [3:0] address ); reg [7:0] memory [0:15]; reg [7:0] datareg; assign data = (WE && !RE && !CE)? datareg : 8'hzz; initial begin memory = 8'h09; // LDA 9H memory = 8'h1A; // ADD AH memory = 8'h1B; // ADD BH memory = 8'h2C; // SUB CH memory = 8'hEC; // OUT memory = 8'hF0; // HLT memory = 8'h01; memory= 8'h02; memory= 8'h03; memory= 8'h04; end always @(address or WE or data && CE) begin if(!CE && WE) begin memory[address] = data; end end always @(address or RE or WE or data && CE) begin if(!CE && !RE && WE) begin datareg = memory[address]; end end endmodule
The register which reads the memory and splits the instruction and address. The instruction is sent to the control unit and the address is written onto the databus.
module instreg( input EI, // Reads the ADDRESS(lower nibble) into databus active(low) input LI, // Reads the OPCODE(upper nibble of the data into control unit) active (low) input clk, input clr, input [7:0] instdatain, output [7:0] instdataout, //Upper nibble - opcode and lower nibble - address output [3:0] address); //Goes to MAR reg [7:0] instdataout; initial begin instdataout = 8'hzz; end always @(posedge clk) begin if(!LI) begin instdataout <= instdatain; end if(!clr) begin instdataout <= 8'hzz; end end assign address = (!EI) ? instdataout[3:0] : 4'hz; endmodule