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Bharath Shashidhar

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Month: May 2017

2nd May 20171st April 2020 bhs011

Verification Suite using SystemVerilog – Functional Coverage – v2.0

Technology, Verification

Systemverilog verification suite of synchronous RAM along with functional coverage, my v1.0 suite can be found here `timescale 1 ns/10 ps module memory(input logic clock ,

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I'm a FPGA design engineer experienced in Very High speed interfaces, SDR, Signal Processing and embedded system design. This blog is dedicated to capture my trials and experiments.

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Recent Posts

  • Installing OpenSource EDA tools on ubuntu
  • Setting up SSH Server on local machine – Ubuntu
  • Verification Suite using SystemVerilog – Functional Coverage – v2.0
  • Parallel Programming – Part 1
  • Cache Simulator v1.0

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