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Bharath Shashidhar

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Month: August 2016

30th August 2016 bhs011

Verification Suite using SystemVerilog

Technology, Verification

  The device under test is the synchronous RAM, `timescale 1 ns/10 ps module memory(input logic clock , // Clock input logic [7:0] address ,

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I'm a FPGA design engineer experienced in Very High speed interfaces, SDR, Signal Processing and embedded system design. This blog is dedicated to capture my trials and experiments.

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  • Installing OpenSource EDA tools on ubuntu
  • Setting up SSH Server on local machine – Ubuntu
  • Verification Suite using SystemVerilog – Functional Coverage – v2.0
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