ASIC Design Flow requires many EDA tools and industry uses some of the advanced EDA tools. For expanding your knowledge on these tools and the
Setting up SSH Server on local machine – Ubuntu
There is way where a local machine can be accessed using ssh once you install OpenSSH. Both the host (server) and Client must be in
Verification Suite using SystemVerilog – Functional Coverage – v2.0
Systemverilog verification suite of synchronous RAM along with functional coverage, my v1.0 suite can be found here `timescale 1 ns/10 ps module memory(input logic clock ,
Parallel Programming – Part 1
I recently started Parallel programming course on Udacity and this blog is my journey through the course. My fascination with new and upcoming technologies goes
Cache Simulator v1.0
Cache simulator is implemented in C. It takes several parameters describing the cache and a trace file describing the memory access for a specific program. The
SAP-1 (Simple As Possible 1) Microprocessor – Part 4
The Testbench and Results The test program was stored in RAM of SAP-1 microprocessor, Load contents of memory location 9H into accumulator 9H contains 01H.
SAP-1 (Simple As Possible 1) Microprocessor – Part 3
Control unit is the heart of any microprocessor, the SAP-1 microprocessor is reset using the clr signal. The program counter is reset to 0000 and
SAP-1 (Simple As Possible 1) Microprocessor – Part 2
This is continuation of my work in implementing the SAP1 processor. This part contains sap1 architecture. Accumulator It is the buffer register which stores intermediate
SAP-1 (Simple As Possible 1) Microprocessor – Part 1
Simple As Possible 1 Architecture Block Diagram SAP-1 is a primitive microprocessor architecture and is good step towards understanding microprocessor working, interaction with memory and
Verification Suite using SystemVerilog
The device under test is the synchronous RAM, `timescale 1 ns/10 ps module memory(input logic clock , // Clock input logic [7:0] address ,